DOC. 00 — RISC-V EDGE-AI ACCELERATOR SoC

Custom silicon for real-time edge intelligence.

Astrixcore designs a low-power, customizable RISC-V accelerator SoC that moves AI inference out of the cloud and onto the sensor — starting with industrial predictive maintenance.

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Core
RISC-V
Focus
Industrial IoT
Stage
Pre-silicon
Path
FPGA → ASIC
SENSORS vibration · temp · vision I/O & SECURITY interfaces · secure boot RISC-V CORE control + application sw AI ACCELERATOR low-power inference ON-CHIP MEMORY weights · activations DECISION
FIG. 1 — SYSTEM BLOCK DIAGRAM REV. A
§ 01 — The Problem

Edge devices need intelligence without cloud-scale compute.

General-purpose processors and cloud round-trips were never designed for always-on, latency-critical, power-constrained sensing.

01

Cloud dependency

Continuous cloud processing adds connectivity and bandwidth requirements that industrial sites often can't guarantee.

02

Latency

Sending sensor or vision data to remote servers can delay decisions that need to happen in milliseconds, not seconds.

03

Power & cost

General-purpose compute is inefficient for the same inference workload run thousands of times a day at the edge.

04

Privacy & reliability

Sensitive operational data often needs to stay local — and edge systems still need to work when connectivity doesn't.

§ 02 — Architecture

A modular SoC, built for FPGA validation first.

Every block is designed to be proven on FPGA, benchmarked against real workloads, and only then carried forward into an ASIC.

01

RISC-V Core

Open, customizable application processor for control and system software — no proprietary ISA lock-in.

02

AI Accelerator

Dedicated matrix/vector engine tuned for compact INT8 / INT4 inference, not general-purpose throughput.

03

On-chip Memory

Weights, activations and fast local data movement, minimizing the overhead that dominates edge inference power.

04

I/O & Interfaces

Direct ADC, sensor and camera connections so raw signal reaches compute with minimal glue logic.

05

Security

Secure boot and a trusted execution path, built in from the first RTL draft rather than bolted on later.

I/O & SECURITY PERIMETER RISC-V CORE AI ACCELERATOR ON-CHIP MEMORY
FIG. 2 — MEMORY-CENTRIC LAYOUT REV. A
§ 03 — Differentiation

What makes the approach different.

Open ISA, no lock-in

RISC-V lets us customize the instruction set for the workload instead of paying rent on someone else's proprietary architecture.

Efficiency-first accelerator

Built for energy-efficient edge inference, not repurposed general-purpose compute running at the wrong operating point.

Hardware/software co-design

Accelerator, memory and data movement are optimized together from day one — not integrated as an afterthought.

Edge-first, real-time

The architecture is built around local, real-time decisions — cloud dependence is the exception, not the default.

Fabless roadmap

Prototype on FPGA, validate real workloads, then move deliberately toward ASIC and IP commercialization.

Fast, low-burn iteration

A small, focused team means design cycles run on months, not fiscal quarters.

§ 04 — Target Markets

Initial focus: industrial edge-AI.

One beachhead first, adjacent markets once the architecture is proven.

INITIAL FOCUS

Industrial Automation

Predictive maintenance, machine health, anomaly detection

02

Robotics

Low-latency perception and sensor processing

03

IoT & Smart Devices

Low-power local intelligence for connected sensors

04

Edge Vision

Local image classification and inspection

05

Automotive / Mobility

Sensor fusion and real-time edge inference

§ 05 — Roadmap

From architecture proof to silicon-ready product.

0–3 MONTHS

Architecture & workload study

RISC-V + accelerator specification.

3–6 MONTHS

RTL development

Verification and FPGA prototype.

6–9 MONTHS

Workload validation

ML benchmarking, power / latency.

9–12 MONTHS

System prototype

Pilot demonstrations in the field.

12–18 MONTHS

ASIC readiness

Physical design, MPW / tape-out planning.

₹50L
18-month funding target
Revenue streams

SoC sales · IP licensing · dev kits · custom accelerators

Initial customers

Semiconductor R&D teams · industrial automation · robotics / IoT developers

Use of funds

Engineering · FPGA & EDA access · lab & testing · prototype iterations

§ 06 — Team & Support

Building a multidisciplinary semiconductor product team.

Core capabilities
  • Digital design
  • VLSI · Verilog / SystemVerilog
  • FPGA
  • AI / ML
  • Embedded systems
  • Verification
Support sought
  • Chip-design mentorship
  • Verification
  • EDA tools & lab access
  • Prototyping
  • Testing & validation
Business support
  • Corporate connections
  • Pilot opportunities
  • Customer introductions
  • Grants / investor connect
“We are developing the concept as an early-stage semiconductor venture, building the required design, verification, AI and systems expertise through mentorship and execution.”
— S KungumaRaj, Founder
§ 07 — Vision

Make specialized AI computing affordable, efficient and accessible at the edge.

FPGA Prototype → Silicon-Ready Accelerator IP → Application-Specific SoC → Scalable Fabless Platform
§ 08 — Contact

Building this with us, or want to talk architecture?

Reach out — whether you're a mentor, a pilot customer, or reviewing this for the iTNT Semiconductor Startup Program.

S KungumaRaj
Founder & Chip Architect

Electronics & Communication Engineering undergraduate designing Astrixcore's RISC-V edge-AI silicon — with hands-on experience in physical design (RTL-to-GDSII), TCAD device simulation, and embedded systems.

RISC-V VLSI · Physical Design TCAD Embedded Systems
Email the founder skrajraj008@gmail.com
Program
iTNT Semiconductor Startup Program ↗

Tamil Nadu's semiconductor incubation & acceleration cohort.